This invention relates to photolithographic methods employed in the manufacture of very large-scale integrated (VLSI) circuits and more specifically to improved methods for generating patterns of photomasks.
Optical lithography has long been a key enabler to the rapid pace of integration that fuels the microelectronics industry. However, the resolution demands of the IC industry have outpaced the introduction of more advanced lithography hardware solutions for many technology generations, making lithographic patterning increasingly difficult and requiring the use of increasingly complex resolution enhancement techniques (RET) to maintain adequate pattern fidelity. As optical lithography is being pushed even closer to its fundamental resolution limit, it is becoming increasingly difficult to implement RET without the benefit of RET-enabling layout restrictions.
While this unprecedented need for communication between the design and wafer-processing communities has been a major factor in the sluggish introduction of RET, the inevitable need to address RET-enabled layouts for sub-90 nm technology nodes also provides an opportunity for broad implementation of design-for-manufacturability (DFM).
To put the discussion on RET and their impact on layout into proper context, it will be helpful to first review some simplified concepts of optical lithography, and then review the exposure tool options for the next two major sub-90 nm technology nodes, and then discuss the basic principles of RET.
For the purpose of this discussion, an optical lithography system can be represented as drawn in FIG. 1A. A coherent plane of light 2, characterized by its wavelength, λ, illuminates a photomask 3, which can be seen as an opaque stencil of the desired pattern. The light passing through the openings in the photomask 3 is focused by lens optics 4 onto an image plane of a wafer 5. At the dimensions in which modern IC lithography operates, the openings in the photomask 3 can be approximated as individual light sources 6, 7 described by their centerline spacing or pitch, P. Since light penetrating neighboring mask openings is coherently related, constructive interference will cause diffraction nodes at any angle for which the geometric pathlength difference between the beams of light is equal to an integer multiple of the wavelength of light, orsin θ=mλ/P  (1)
The maximum diffracted angle that a projection lens can capture and use for image formation is defined as the maximum numerical aperture (NA) of the lens. Since one has to capture at least one diffracted order (the 0th order contains no spatial information), equation 1 can be rewritten as,Pmin=λ/NA  (2)
Or, in the more popular approximation assuming the minimum feature size, R, is simply P/2,Rmin=0.5λ/NA  (3)
How close any given lithography process comes to this theoretical resolution limit is commonly expressed by the Rayleigh factor k1,R=k1λ/NA  (4)
Equation 4 provides a coherent approximation to conventional optical lithography. As is apparent from equation 4, the resolution is proportional to λ, and inversely proportional to NA. These two physical quantities are constraints on the minimum feature size R that can be printed, also referred to as the “half pitch” (P/2) according to the above relation.
In addition to defining the fundamental resolution limit of a patterning system, the Rayleigh factor is also used as a unitless measure of lithographic challenge, i.e., the quantity k1 which is defined ask1=Dimension(NA/λ)  (5)expresses how difficult it is to resolve a certain dimension with a given lithography tool and is often used in lieu of the feature size R.
The role of depth of focus and the equations governing it will now be discussed. As illustrated in FIG. 1A, the image on the wafer, at the resolution limit, is formed by the interference of the 0th and 1st diffracted orders. Since the 0th diffracted order traverses the optical system perpendicular, i.e. along the center axis of the optical system, a pathlength difference ΔPL is introduced relative to the higher diffracted orders. This pathlength difference changes as a function of the vertical image plane displacement z according to the relation:ΔPL=z−z cos θ  (6)
The change in pathlength difference causes the phase relationship between the beams to vary. Rayleigh defines the depth of focus (DOF) as the vertical displacement for which the pathlength difference between the two beams is λ/4, leading to the relation:DOF=(λ/4)(1/(1−cos θ))  (7)
After some trigonometric contortions and substitution of NA for sin θ, equation 7 reduces to the commonly quoted DOF equation,DOF=λ/(2NA2)  (8)highlighting the inverse square dependence of DOF and NA. This rapid loss of DOF in relation to NA is one of the fundamental limitations of high-NA lithography.
The role played by the wavelength of the illumination source will now be discussed. The direct correlation of lithographic resolution and illumination wavelength, as stated in equation 4, has traditionally been the main resolution reduction enabler.
TABLE 1Lithography wavelengths and their applicability, *126nm lithography is no longer considered a viable optionIntendedYear ofSourceλ (nm)λ ratioResolutionIntrod.G-line436micronI-line365.83half-micron1984KrF248.68quarter-micron1989ArF193.78100 nm-node 2001F2157.8165 nm-nodeExpect2004Ar2126.8045 nm-node*
Table 1 lists past, present, and future lithography wavelengths, their resolution in terms of applicable product, and their year of introduction. This short list makes a few important points: there are only a few distinct wavelengths that can be used for lithography; that an end of the available light sources is coming quickly; and the ratio of wavelength reduction in most cases is not even enough to support one linear shrink of 70%.
Not captured in Table 1 is the immense financial and time investment in introducing not only an exposure tool at a new wavelength but a full patterning solution including resist and etch processes. As the drive to develop new exposure tools at shorter wavelengths continues, severe physical barriers to implementation arise in: insufficient light intensity requiring super-sensitive chemically amplified resist systems, increased light absorption forcing more exotic optical materials and tighter cleanliness specifications on all optical components including the photomask, and ultimately, the need to operate in vacuum with reflective optics.
The determination of numerical aperture (NA) and its importance in optical lithography are now discussed. Being defined as the sine of an angle, the mathematical limit of the numerical aperture (NA) is 1. Controlling critical parameters such as aberrations and focal plane flatness over large areas during lens manufacturing has made the introduction of NAs larger than 0.7 very difficult. Finally, the inverse quadratic relationship between DOF and NA (equation 8) make it challenging to manufacture with NAs much above 0.7 (for a NA of 0.7 the DOF is roughly 2λ, requiring extreme control of wafer flatness, reduction of process induced topography, and very tight focus control in the exposure). Nonetheless, state of the art exposure tools use NAs of 0.75 in wafer production and 0.85 NA tools are soon to be introduced.
Trends in the adoption of new lithography solutions in manufacturing will now be discussed. Table 2 shows how lithography solutions have evolved as smaller features sizes are demanded. As expected, wavelength has been decreasing and NA has been increasing. However, k1 has been continuously declining in spite of tooling improvements; i.e., lithography has been loosing ground due to ever harder technology generations. Finally, for each technology generation two distinct lithography solutions can be identified, a very aggressive, low k1 development phase followed by a somewhat relaxed manufacturing phase.
TABLE 2λ/NA solutions for recent technology nodes [1], illustratingthe constant erosion of k1 for both technology development (Dev.)and manufacturing (Man.) *Potential SolutionITRSMan.Min.Dev.Man.Dev.Man.NodeYearPitchλ/NAλ/NAk1k11801999500248/.50248/.75.50.761302001300248/.75193/.75.45.58902003214193/.75193/.85.42.48652005160193/.85157/.85*.35(.43)452007130157/.85*Unknown(.35)Unknown
Table 2 clearly highlights the need for a lithography solution that can deliver k1 factors smaller than 0.5.
Two-beam imaging techniques will now be discussed, as an example of strong-RET. If, as illustrated in FIG. 1B, one were able to ‘push back’ one of light sources approximating the mask openings, 6, 7 by ½λ, to obtain mask openings 161,171 one would obtain a very different diffraction pattern, which more spatially confined in the horizontal imaging plane.
Since the first interference now occurs at an angle that adds ½ λ pathlength difference (rather than 1 λ for conventional lithography) the minimum set of diffracted orders required to form an image for a given pitch are much closer to the center of the imaging lens. For a given NA, the ultimate resolution, in terms of half-pitch, is now described bya. Rmin=0.25λ/NA  (9)
From an examination of equations 4 and 9, the Rayleigh factor k1 here is 0.25. In addition, no constructive interference occurs at the 0° angle (the light sources are ½ λ out of phase), so the perpendicular beam is eliminated and with it the DOF limitations of equation 8. Therefore, two-beam imaging provides 50% resolution improvement and significantly enhanced DOF.
One popular means of achieving two-beam imaging is shown in FIG. 1C. To obtain the ½ λ phase offset, alternating phase shifted mask lithography (altPSM) manipulates the topography of the mask 14 to vary the respective etch depth of juxtaposed openings 18, 19 in the light transmitting medium 13 of the mask 14 by anEtch Depth=0.5λ/(n−1)  (10)where n is the refractive index of the mask substrate, typically around 1.4.
By varying the etch depth of juxtaposed mask openings in this manner, the light traversing the two openings will exhibit a phase difference of 180 degrees. Taking this approach a step further, a technique known as phase coloring is performed. In the phase coloring process, a plurality of “intrusion pairs” of juxtaposed mask openings which exhibit a 180 degree phase difference are formed on opposite sides of a critical dimensioned feature of the chip layout. The intrusion pair includes a zero degree phase region on one side, and a 180 degree phase region on the opposite side of the critical dimensioned feature.
An example of use of the above-described techniques is illustrated in FIGS. 2A through 3D. FIG. 2A is a plan view of a layout 10 of a feature to be printed, which cannot be printed with sufficient accuracy when employing only non-phase shifted mask techniques. The transistor layout 10 has a wide rectangular head T1, shoulders 10S, and a narrower vertical leg V1. The vertical leg V1 is formed as a narrow linewidth feature having a sub-cutoff dimension, i.e., a dimension smaller than the minimum feature size of traditional photolithography for the system in use. The head T1 is wider than the cutoff dimension. To achieve the desired exposure pattern in the resist, images are projected onto the resist layer of a substrate using two different masks in sequence. The first mask is a dark field alternating phase shift mask 15. The first mask includes intrusion pairs of zero degree and 180 degree phase-shifting regions 12′, 14′ respectively, and is used for making critical dimensioned exposure patterns on the wafer. The first mask 15 is opaque in all areas 13 except where the intrusion pairs 12′, 14′ are located. The second mask 16 is a bright field trim mask, which is transparent in all areas 17 except where block mask patterns 18 are present. The second mask 16 is used to expose the resist a second time after the resist is exposed using the first mask 15. This technique is used with a positive resist in which exposed areas are developed away, leaving the unexposed areas to remain as the desired pattern.
FIG. 2B illustrates a dark field altPSM mask 15 and FIG. 2D illustrates a block pattern of a bright field trim mask 16 corresponding thereto. FIGS. 2C and 2E illustrate corresponding patterns in the resist after lithographic exposure with the masks 2B and 2D, respectively. As illustrated in FIGS. 2C and 2E, the lithographic exposures have resulted in resist patterns 12″, 14″, and 17′ that have rounded corners instead of the original block shapes, due to the resolution limits described above. FIG. 2F shows the combined lithographic exposure pattern 10′ that results after exposure with the dark field altPSM mask 15 and another exposure with the bright field trim mask 16. As illustrated in FIG. 2F, the resulting exposure 10′ reasonably approximates the desired pattern 10 of FIG. 2A.
FIGS. 3A through 3D illustrate a sequence of steps performed in a prior art method of generating patterns of an altPSM mask and a block (trim) mask corresponding thereto. This process takes advantage of the constructive interference of light to double the achievable resolution of the optical lithography system. The light interference is created by selectively manipulating the topography of the photomask to introduce an appropriate path-length difference in the imaging light.
FIG. 3A illustrates a transistor polysilicon shape 20 to be patterned by a dual exposure altPSM method. Each of the sample polysilicon shapes 20 reflects a shape similar to that of the desired transistor shape 10 shown in FIG. 2A, having a sub-cutoff dimension to be patterned by an altPSM mask having a pair of inverse phase-shifting regions 22, 24 of zero degrees and 180 degrees phase shift on opposite sides of the transistor shape to be patterned. In addition to having inverse phases assigned on opposite sides of the critical dimensioned feature, the phase shapes or regions need to obey a variety of lithographic, mask manufacturability, and design rules governing their size and spacings. Note that the design of an altPSM layout, as shown, requires that the inverse phase shifting shapes be located on opposing sides of the sub-cutoff dimension feature, such that one of the two inverse phase shapes is assigned a phase shift that is 180 degrees out of phase from that of the phase shape on the opposite side of the sub-cutoff dimension feature.
The key to this specific example is the fact that two phase shift patterns need to be defined for each critical segment of a layout structure. As shown in FIG. 2A, both the zero degree phase shapes 22 and the 180 degree phase shapes 24 have to be defined as patterns in a data set representing the mask, even though no special processing is required to define zero degree phase shapes 22 in the mask.
Referring to FIG. 3B, this figure is an illustration of a dark field alternating PSM layout. The sample polysilicon layout is still shown at 20 and the block mask 26 is illustrated by the crosshatched areas.
When the resist is then exposed, once with the altPSM mask of FIG. 3A and once with the block trim mask of FIG. 3B, the final exposure pattern will be formed in the photo-resist as the difference between the shadow cast by the block pattern and the interference pattern produced by the zero degree and 180 degree phase shapes.
One approach to improve lithographic performance has been to optimize altPSM parameters. An example of this is illustrated in FIGS. 3C and 3D. In FIG. 3C an optimized altPSM layout is shown having phase extensions 30 (bottom of 180 degree portion) and phase end hammerheads 32 (top of 180 degree portion). This specific example is optimized to the situation where a gap between two primary features is filled with a common block shape being entirely covered by the block edge, and the phase edge is extended past its regular position. To further optimize the layout and preserve layout density, the top edge is not linearly extended, but hammerheads are added to counteract phase end shortening. FIG. 3D is a block mask similar to FIG. 3B.
The fundamental lithographic principles of the double exposure processes illustrated in FIGS. 2A through 2F and 3A through 3D dictate a simple layout rule for the phase and block shapes. This rule provides that the desired layout pattern to be provided on the wafer should be constructed as the Boolean difference between the block shapes and the phase shapes of the pair of altPSM mask and trim mask. Another way of expressing this rule is that wherever there is a block shape, there also needs to be a phase shape. Violation of this rule results in a residual resist image on the wafer, or, in other words, unexposed resist that can cause defects on the wafer.
The constraints of manufacturability and the fundamental lithographic resolution for both phase shifting patterns and block patterns of a mask require that such patterns be constrained to certain minimum width and spacing. While block masks and phase masks must each conform to their own set of unique manufacturability and lithography constraints, problems arise when the block mask is legalized independently from the phase-shifting mask, or vice versa. This is because the different processes required to manufacture a block mask, as compared to a phase-shifting mask, and the different parameters with each type of mask is used to expose a resist layer of a substrate, require that different minimum widths and minimum spaces be designated for each type of mask.
FIG. 4 illustrates process steps in the generation of phase shapes of an altPSM mask and block shapes of a corresponding block (trim) mask for use in a dual exposure method. In a first step 101 of the prior art method of FIG. 4, design data for a circuit layout (e.g. from a circuit design program) is input to a processor. Next, in step 102, all critical segments of the layout are identified. Then, the method progresses to the next step 103 of creating basic phase shapes, i.e. the rough outlines of the polygons which will receive the phase information are defined
In the next step 104, layout violations are removed from the generated phase shapes by a legalization process. Legalizing is the process of checking and adjusting or fixing patterns so that they conform to minimum space rules between features and minimum width rules, which are imposed by the lithography and mask manufacturing process After this step, the phase regions are then colored (step 105).
Thereafter, the shapes of the block mask are generated (step 106), and the block mask including those shapes is then legalized, in step 111. A check is then made, in decision block 112, to determine if the shapes of the phase-shifting mask are correctly adjusted for the shapes of the block mask that has just been generated. Very often, they are not, in which case, the result of the decision block 112 is “No”, and the process resumes again at step 104 with legalizing the shapes of the phase-shifting mask. In time, new block shapes may be added when step 111 is encountered again to legalize the shapes of the block mask. Accordingly, the prior art method shown in FIG. 4 is a circular method in which the shapes of the block mask depend on the shapes of the phase-shifting mask, but the shapes of the phase-shifting mask also depend on the shapes of the block mask.
A problem with the prior art method of FIG. 4 is the need to continually modify the layout by going back to the redefinition of critical segments. While the optimization altPSM parameters as provided above show great promise in improving lithographic performance, the circular definition of mask features challenges the capabilities of current tools to generate suitable altPSM and block mask combinations. As illustrated in FIG. 4, the details of the phase shape design depend on critical layout segments, and the details of the block mask design depend on both critical layout segments and the exact phase design, but the exact phase design also depends on details of the block mask design.
Therefore, a new approach is needed that can address the need for a better and more cost and time efficient method of generating mask patterns. The present invention addresses these concerns by improving the parameter definition and design flow of generating altPSM mask and block mask pairs to generate lithographically optimized and logically correct altPSM layouts.
FIGS. 5A through 11 illustrate steps in a prior art method for generating block patterns and phase-shifting patterns of a block (trim) mask and an altPSM mask for use in a dual exposure method for defining critical dimensioned features in a resist pattern of a substrate.
As shown in FIG. 5A, a feature 401 and critical dimensioned features 402 of a circuit layout are identified according to step 102 of the method shown in FIG. 4. Then, as shown in FIG. 5B, a set of phase regions 502 are then generated for the phase shifting mask, the phase regions 502 lying on each side of the critical dimensioned features 504 to be patterned. Thereafter, the phase regions are legalized, resulting in one larger phase region 602, as shown in FIG. 6, because the prior spacing between the phase regions 502 did not conform to rules for minimum spacing between adjacent phase regions.
Then, a step of coloring the legalized phase regions is conducted, as shown in FIG. 7, in that the shapes 702 are assigned zero degree phase and shapes 704 are assigned 180 degree phase. Next, as shown in FIG. 8, the shapes of the block mask are designed, as shown by the rectangular outlines 802, 804 and 806 that now appear, which overlap the phase patterns in FIG. 8. Of course, the rectangular block mask shapes, and the phase patterns belong to a block mask and an altPSM mask that will be utilized in a dual exposure method as described above relative to FIGS. 2A through 2F. The reason that the shapes of the block mask overlap the shapes of the phase mask rather than entirely enclosing them is because the interference pattern in the completed altPSM mask between the zero degree and the 180 degree phase shapes actually drops the transmitted intensity to a negligible level outside the boundaries of the block mask shapes.
Next, as shown in FIG. 9, the block mask shapes are now legalized, such that the pattern of block shapes are checked for conformity with rules regarding minimum block shape width and minimum spacing between block shapes. When neighboring block shapes are spaced more closely than the minimum width, the mask rule requires that the subminimum width space between them be filled with another block shape. This result is illustrated in FIG. 9 by the addition of the block shape 901 between the block shapes 902 and 903.
At this time, it is appropriate to comment on the accuracy of the resulting patterns generated by the prior art method of FIG. 4. Thus far, the shapes of the phase mask have been generated and legalized, and the shapes of the block mask have been generated and legalized thereafter. However, it is apparent that there is yet much to do before the shapes of both masks are finalized. The shapes of the altPSM mask must now be legalized again for conformity with the rules on minimum width and minimum spacing between respective phase shapes. In addition, once that legalization is performed, the block shapes must also be adjusted and legalized again.
One possible way of reducing the cycle of legalizing the phase shapes relative to the block shapes, and then legalizing the block shapes again relative to the changed phase shapes, would be to generate the phase shapes in the first instance based on predictions of the block mask shapes to be generated thereafter. However, the actual layouts of different chips present many complicated topologies in which predicting the geometry of the block mask shapes is difficult to do accurately based on the phase patterns to be generated.
Next, as shown in FIG. 10, the shapes of the phase mask are now adjusted relative to the block mask shapes that have been created, such that certain of the phase shapes are now enlarged in this step. Thus, the shapes 1001 and 1002 which extend outside the block shape 1006 are now added to counteract phase-end shortening when the masks are used to print the critical dimensioned features 1008, and a phase shape 1004 at zero degree phase is added which adjoins the existing zero degree phase shape 1003 in the location of the added block mask shape 1010.
However, after this step has been performed, it is apparent that sufficient changes may have been made to the shapes of the phase mask that the changed shape pattern may need to be legalized again for conformity with the minimum width and minimum spacing rules. Hence, control is now returned again to step 104 of the method illustrated in FIG. 4. As shown in FIG. 11, this step now results in a new shape 1102 being added between the shapes 1104 and 1106 of the phase mask, where minimum spacing did not exist before between those shapes 1104 and 1106.
The shortcomings of the prior art having been described, it would be desirable to provide a more efficient, more reliable method of generating patterns of a phase mask and of a block mask for use in performing dual exposure altPSM lithography to define critical dimensioned features in a resist on a substrate.